The present invention is directed generally to electronic devices whose functional length scales are measured in nanometers, and, more particularly, to configurable transistors based on crossed nanometer-scale wires. Such configurable transistors find use, for example as nanometer-scale memories, and, more particularly, as flash memories at a nanometer scale.
Flash memories are well-known; see, for example, a discussion of NAND flash memories by Jung-Dal Choi et al, xe2x80x9cHighly Manufacturable 1 Gb NAND Flash Using 0.12 xcexcm Process Technologyxe2x80x9d, International Electron Devices Meeting, Dec. 2-5, 2001, as reprinted in IEDM Technical Digest, pp. 2.1.1-2.1.4. All such flash memories are fabricated at the micrometer scale, using lithographic processes. By xe2x80x9cmicrometerxe2x80x9d scale is meant that the functional dimension is measured in micrometers (typically about 1 micrometer down to tenths of micrometers).
The density of such micrometer-scale flash memories is insufficient for ever-increasing needs for more memory in less area/volume.
Nanometer-scale memory devices are also known; see, for example, U.S. Pat. No. 6,128,214, entitled xe2x80x9cMolecular Wire Crossbar Memoryxe2x80x9d, issued to Philip J. Kuekes et al on Oct. 3, 2000, and assigned to the same assignee as the present invention, the contents of which are incorporated herein by reference.
Nanometer-scale semiconductor devices, such as field effect transistors (FETs), p-n diodes, bipolar junction transistors, and complementary inverters, are also known; see, e.g., (1) application Ser. No. 09/699,269, filed Oct. 26, 2000, now U.S. Pat. No. 6,559,468, issued May 6, 2003, which is a divisional application of application Ser. No. 09/280,188, filed Mar. 29, 1999, now abandoned, entitled xe2x80x9cMolecular Wire Transistor (MWT)xe2x80x9d and filed in the names of Philip J. Kuekes et al and assigned to the same assignee as the present application; Yu Huang et al, xe2x80x9cLogic Gates and Computation from Assembled Nanowire Building Blocksxe2x80x9d, science, Vol. 294, Issue 5545, pp. 1313-1317 (Nov. 9, 2001); and (3) Adrian Bachtold et al, xe2x80x9cLogic Circuits with Carbon Nanotube Transistorsxe2x80x9d, Science. Vol. 294, Issue 5545, pp. 1317-1320 (Nov. 9, 2001). However, these references do not disclose memory devices.
Thus, there remains a need for a nano-scale flash memory, employing nano-scale transistor devices.
In accordance with the embodiments disclosed herein, a nano-scale flash memory is provided, comprising:
(a) source and drain regions in a plurality of approximately parallel first wires of nanometer-scale diameter, the first wires comprising a semiconductor material, the source and drain regions separated by a channel region;
(b) gate electrodes in a plurality of approximately parallel second wires of nanometer-scale diameter, the second wires comprising either a semiconductor material or a metal, the second wires crossing the first wires at a closest distance of nanometer scale dimensions between the second wires and the first wires, and at a non-zero angle over the channel regions, to form an array of nanoscale transistors; and
(c) a hot electron trap region, associated with each intersection of the first wires with the second wires, for controlling conductance of an associated transistor.
The disclosed embodiments solve the problem of making a flash memory at a very high density, in which the spacing between bits is on the order of a few nanometers. An extremely regular and therefore inexpensive assembly process is used.
Also in accordance with the embodiments disclosed herein, a configurable nanowire transistor is provided, comprising (a) a pair of crossed nanowires, one of the nanowires comprising a semiconductor material having a first conductivity and the other nanowire comprising either a metal or a second semiconductor material, and (b) a dielectric or molecular species to trap and hold hot electrons. The nanoscale wire transistor either forms a configurable transistor or a switch memory bit that is capable of being set by application of a voltage that is larger in absolute magnitude than any voltage at which the transistor operates. The pair of wires cross at a closest distance of nanometer scale dimensions and at a non-zero angle.
A method is provided for fabricating the nano-scale wire transistor, which comprises providing a first nano-wire, providing a second nano-wire, causing the first and second nano-wires to cross at a closest distance of nanometer scale dimensions and at a non-zero angle, and providing the hot electron trap region associated with the transistor.
Further, a crossbar array of the foregoing crossed-wire devices is provided.